LTC4261/LTC4261-2

42612fd

For more information www.linear.com/LTC4261

PGI (Pin 1/Pin 22): Power Good Input. This pin along with

the PGI check timer serves as a watchdog to monitor the

power-up of the DC/DC converter. The PGI pin must be low

before the PGI check timer expires, otherwise the GATE

pin pulls down and stays latched and a power bad fault

is logged into the FAULT register. The PGI timer is started

after the second power good is latched and its delay is

equal to four times the start-up debounce delay. Connect

to V

if unused.

PGIO (Pin 28/Pin 21): General Purpose Input/Output.

Open-drain logic output and logic input. Defaults to pull

low a timer delay after the PG pin goes low to indicate a

second power good output. Configure according to Table 6.

RAMP (Pin 18/Pin 12): Inrush Current Ramp Control

Pin. The inrush current is set by placing a capacitor (C

)

between the RAMP pin and the drain terminal of the FET.

At start-up, the GATE pin is pulled up by I

GATE(UP)

until the

pass transistor begins to turn on. A current, I

RAMP

, then

flows through C

to ramp down the output voltage V

OUT

The value of I

RAMP

is controlled by the SS pin voltage.

When the SS pin reaches its clamp voltage (2.56V), I

RAMP

= 20µA. The ramp rate of V

OUT

and the load capacitor C

set the inrush current: I

INRUSH

= (C

) • I

RAMP

SCL (Pin 6/Pin 3): Serial Bus Clock Input. Data at the

SDAI pin is shifted in and data at the SDAO pin is shifted

out on rising edges of SCL. This is a high impedance pin

that is generally connected to the output of the incoming

optoisolator driven by the SCL port of the master controller.

An external pull-up resistor or current source is required.

Pull up to INTV

if unused.

SDAI (Pin 5/Pin 2): Serial Bus Data Input. This is a high

impedance input pin used for shifting in command bits,

data bits and SDAO acknowledge bits. An external pull-up

resistor or current source is required. Normally connected

to the output of the incoming optoisolator that is driven

by the SDA port of the master controller. If the master

controller separates SDAI and SDAO, data read at SDAO

needs to be echoed back to SDAI for proper I

C commu-

nication. Pull up to INTV

if unused.

SDAO (Pin 4/Pin 1): Serial Bus Data Output. Open-drain

output used for sending data back to the master controller

or acknowledging a write operation. An external pull-up

resistor or current source is required. Normally connected

to the input of the outgoing optoisolator that outputs to

the SDA port of the master controller. In the single-wire

broadcast mode, the SDAO pin sends out selected data

that is encoded with an internal clock.

SENSE (Pin 14/Pin 9): Current Limit Sense Input. Load

current through the external sense resistor (R

) is moni-

tored and controlled by an active current limit amplifier

to 50mV/R

. Once V

SENSE

reaches 50mV, a circuit breaker

timer starts and turns off the pass transistor after 530µs. In

the event of a catastrophic short circuit, if V

SENSE

crosses

250mV, a fast response comparator immediately pulls the

GATE pin down to control the current of the N-channel FET.

SS (Pin 19/Pin 13): Soft-Start Input. Connect a capaci

tor to this pin to control the rate of rise of inrush current

(dI/dt) during start-up. An internal 10µA current source

charging the external soft-start capacitor (C

) creates

a voltage ramp. This voltage is converted to a current to

charge the GATE pin up and to ramp the output voltage

down. The SS pin is internally clamped to 2.56V limiting

GATE(UP)

to 11.5µA and I

RAMP

to 20µA. If the SS capacitor

is absent, the SS pin ramps from 0V to 2.56V in 220µs.

TMR (Pin 20/Pin 14): Delay Timer Input. Connect a capaci

tor (C

TMR

) to this pin to create timing delays at start-up,

when power good outputs pull down, during PGI check

and when auto-retrying after faults (except overvoltage

fault). Internal pull-up currents of 10µA and 5µA and

pull-down currents of 5µA and 12mA configure the delay

periods as multiples of a nominal delay of 256ms • C

TMR

µF. Delays for start-up and auto-retry following undervolt-

age or power bad fault are the same as the nominal delay.

Delays for sequenced power good outputs are twice of the

nominal delay

. Delays for

PGI check and auto-retry fol

lowing overcurrent fault are four times the nominal delay.

(SSOP/QFN)

PIN FUNCTIONS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 33 34

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ADC 2 Specifications Page 9

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