AD7991/AD7995/AD7999
Rev. B | Page 17 of 28
THEORY OF OPERATION
The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit,
single-supply, 4-channel ADCs. Each part can be operated from
a single 2.35 V to 5.5 V supply.
The AD7991/AD7995/AD7999 provide the user with a 4-channel
multiplexer, an on-chip track-and-hold, an ADC, and an I
2
C-
compatible serial interface, all housed in an 8-lead SOT-23 package
that offers the user considerable space-saving advantages over
alternative solutions.
The AD7991/AD7995/AD7999 normally remains in a power-
down state while not converting. Therefore, when supplies are
first applied, the part is in a power-down state. Power-up is initiated
prior to a conversion, and the device returns to the power-down
state upon completion of the conversion. This automatic power-
down feature allows the device to save power between conversions.
This means any read or write operations across the I
2
C interface
can occur while the device is in power-down.
CONVERTER OPERATION
The AD7991/AD7995/AD7999 are successive approximation
ADCs built around a capacitive DAC. Figure 18 and Figure 19
show simplified schematics of the ADC during its acquisition
and conversion phases, respectively. Figure 18 shows the ADC
during its acquisition phase: SW2 is closed, SW1 is in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on V
IN
. The source driving the
analog input needs to settle the analog input signal to within
one LSB in 0.6 s, which is equivalent to the duration of the
power-up and acquisition time.
06461-020
CAPACITIVE
DAC
V
IN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 19, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The input is disconnected when the con-
version begins. The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code. Figure 20 shows
the ADC transfer function.
06461-021
V
IN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
CAPACITIVE
DAC
Figure 19. ADC Conversion Phase
ADC Transfer Function
The output coding of the AD7991/AD7995/AD7999 is straight
binary. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for
the AD7991/AD7995/AD7999 is V
REF
/4096, V
REF
/1024, and
V
REF
/256, respectively. Figure 20 shows the ideal transfer
characteristics for the AD7991/AD7995/AD7999.
111 ... 111
111 ... 110
111 ... 000
ADC CODE
AGND + 1 LSB
ANALOG INPUT
0V TO REF
IN
AD7991 1 LSB = REF
IN
/4096
AD7995 1 LSB = REF
IN
/1024
AD7999 1 LSB = REF
IN
/256
+REF
IN
– 1 LSB
011 ... 111
000 ... 010
000 ... 001
000 ... 000
06461-022
Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics
(14 pages)
(118 pages)
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