ADC UD-50 Specifications download pdf (Page 30)

AD9259 Data Sheet

Rev. E | Page 30 of 52

05965-093

NUMBER OF SDIO PINS CONNECTED TOGETHER

(V)

1.715

1.720

1.725

1.730

1.735

1.740

1.745

1.750

1.755

1.760

1.765

1.770

1.775

1.780

1.785

1.790

1.795

1.800

0302010 40 50 60 70 80 90 100

Figure 57. SDIO Pin Loading

If the user chooses not to use the SPI, these dual-function pins

serve their secondary functions when the CSB is strapped to

AVDD during device power-up. See the Theory of Operation

section for details on which pin-strappable functions are

supported on the SPI pins.

For users who wish to operate the ADC without using the

SPI, remove any connections from the CSB, SCLK/DTP, and

SDIO/ODM pins. By disconnecting these pins from the control

bus, the ADC can function in its most basic operation. Each

of these pins has an internal termination that floats to its

respective level.

DON’T CARE

DON’T CAREDON’T CARE

DON’T CARE

SDIO

SCLK

CSB

CLK

R/W W1 W0 A12 A11 A10 A9 A8 A7

D5 D4 D3 D2 D1 D0

05965-012

Figure 58. Serial Timing Details

Table 15. Serial Timing Definitions

Parameter Timing (Minimum, ns) Description

5 Setup time between the data and the rising edge of SCLK

2 Hold time between the data and the rising edge of SCLK

CLK

40 Period of the clock

5 Setup time between CSB and SCLK

2 Hold time between CSB and SCLK

16 Minimum period that SCLK should be in a logic high state

16 Minimum period that SCLK should be in a logic low state

EN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 58)

DIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 58)

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 51 52

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ADC UD-50 Specifications Page 30

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