ADC ICX-250 Specifications

October 2008 Rev 4 1/197ST72325xx8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS,5 timers, SPI, SCI, I2C interfaceFeatures Memories– 16K to 60K dual vol

ST72325xx10/197Figure 4. 44/42-Pin LQFP Package Pinouts MCO / AIN8 / PF0BEEP / (HS) PF1(HS) PF2OCMP1_A / AIN10 / PF4ICAP1_A / (HS) PF6EXTCLK_A / (HS)

ST72325xx100/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.8 Register DescriptionCONTROL REGISTER (SPICR)Read/WriteReset Value: 0000 xxxx (0xh)Bit 7 = S

ST72325xx101/197SERIAL PERIPHERAL INTERFACE (Cont’d)CONTROL/STATUS REGISTER (SPICSR)Read/Write (some bits Read Only)Reset Value: 0000 0000 (00h)Bit 7

ST72325xx102/197SERIAL PERIPHERAL INTERFACE (Cont’d)Table 21. SPI Register Map and Reset Values Address(Hex.)RegisterLabel765432100021hSPIDRReset Valu

ST72325xx103/19710.6 SERIAL COMMUNICATIONS INTERFACE (SCI)10.6.1 IntroductionThe Serial Communications Interface (SCI) offersa flexible means of full-

ST72325xx104/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)Figure 63. SCI Block DiagramWAKEUPUNITRECEIVERCONTROLSRTRANSMITCONTROLTDRE TC RDRF IDLE OR NF

ST72325xx105/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.4 Functional DescriptionThe block diagram of the Serial Control Interface,is shown in Fig

ST72325xx106/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.4.2 TransmitterThe transmitter can send data words of either 8 or9 bits depending on the

ST72325xx107/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.4.3 ReceiverThe SCI can receive data words of either 8 or 9bits. When the M bit is set, w

ST72325xx108/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)Figure 65. SCI Baud Rate and Extended Prescaler Block DiagramTRANSMITTERRECEIVER SCIETPRSCIERP

ST72325xx109/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)Framing ErrorA framing error is detected when: – The stop bit is not recognized on reception a

ST72325xx11/197Figure 5. 32-Pin LQFP/DIP Package Pinouts ICCDATA / MISO / PC4AIN14 / MOSI / PC5ICCCLK / SCK / PC6AIN15 / SS / PC7 (HS) PA3AIN13 / OCMP

ST72325xx110/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.4.7 Parity ControlParity control (generation of parity bit in transmis-sion and parity c

ST72325xx111/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.4.9 Clock Deviation CausesThe causes which contribute to the total deviationare:–DTRA: De

ST72325xx112/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.5 Low Power Modes 10.6.6 InterruptsThe SCI interrupt events are connected to thesame inte

ST72325xx113/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)10.6.7 Register DescriptionSTATUS REGISTER (SCISR)Read OnlyReset Value: 1100 0000 (C0h)Bit 7 =

ST72325xx114/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)CONTROL REGISTER 1 (SCICR1)Read/WriteReset Value: x000 0000 (x0h)Bit 7 = R8 Receive data bit 8

ST72325xx115/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)CONTROL REGISTER 2 (SCICR2)Read/WriteReset Value: 0000 0000 (00h)Bit 7 = TIE Transmitter inter

ST72325xx116/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)DATA REGISTER (SCIDR)Read/WriteReset Value: UndefinedContains the Received or Transmitted data

ST72325xx117/197SERIAL COMMUNICATIONS INTERFACE (Cont’d)EXTENDED RECEIVE PRESCALER DIVISIONREGISTER (SCIERPR)Read/WriteReset Value: 0000 0000 (00h)All

ST72325xx118/197SERIAL COMMUNICATION INTERFACE (Cont’d)Table 24. SCI Register Map and Reset Values Address(Hex.)RegisterLabel765432100050hSCISRReset V

ST72325xx119/19710.7 I2C BUS INTERFACE (I2C)10.7.1 IntroductionThe I2C Bus Interface serves as an interface be-tween the microcontroller and the seria

ST72325xx12/197PIN DESCRIPTION (Cont’d)For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 142.Legend / Abbrevia

ST72325xx120/197I2C BUS INTERFACE (Cont’d)Acknowledge may be enabled and disabled bysoftware.The I2C interface address and/or general call ad-dress ca

ST72325xx121/197I2C BUS INTERFACE (Cont’d)10.7.4 Functional DescriptionRefer to the CR, SR1 and SR2 registers in Section10.7.7. for the bit definition

ST72325xx122/197I2C INTERFACE (Cont’d)How to release the SDA / SCL linesSet and subsequently clear the STOP bit whileBTF is set. The SDA/SCL lines are

ST72325xx123/197I2C BUS INTERFACE (Cont’d)Master TransmitterFollowing the address transmission and after SR1register has been read, the master sends b

ST72325xx124/197I2C BUS INTERFACE (Cont’d)Figure 69. Transfer SequencingLegend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledg

ST72325xx125/197I2C BUS INTERFACE (Cont’d)10.7.5 Low Power Modes10.7.6 InterruptsFigure 70. Event Flags and Interrupt GenerationNote: The I2C interrup

ST72325xx126/197I2C BUS INTERFACE (Cont’d)10.7.7 Register DescriptionI2C CONTROL REGISTER (CR)Read / WriteReset Value: 0000 0000 (00h)Bit 7:6 = Reserv

ST72325xx127/197I2C BUS INTERFACE (Cont’d)I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)Bit 7 = EVF Event flag. This bit is set by

ST72325xx128/197I2C BUS INTERFACE (Cont’d)Bit 1 = M/SL Master/Slave.This bit is set by hardware as soon as the interfaceis in Master mode (writing STA

ST72325xx129/197I2C BUS INTERFACE (Cont’d)I2C CLOCK CONTROL REGISTER (CCR) Read / WriteReset Value: 0000 0000 (00h)Bit 7 = FM/SM Fast/Standard I2C mod

ST72325xx13/19717 13 13 11 6 PD4/AIN4 I/O CTX X X X X Port D4 ADC Analog Input 418 14 14 12 7 PD5/AIN5 I/O CTX X X X X Port D5 ADC Analog Input 519 -4

ST72325xx130/197I2C BUS INTERFACE (Cont’d)I2C OWN ADDRESS REGISTER (OAR1) Read / WriteReset Value: 0000 0000 (00h)7-bit Addressing ModeBit 7:1 = ADD[7

ST72325xx131/197I²C BUS INTERFACE (Cont’d)Table 25. I2C Register Map and Reset Values Address(Hex.)Register Label765 4 32100018hI2CCRReset Value 0 0P

ST72325xx132/19710.8 10-BIT A/D CONVERTER (ADC)10.8.1 IntroductionThe on-chip Analog to Digital Converter (ADC) pe-ripheral is a 10-bit, successive ap

ST72325xx133/19710-BIT A/D CONVERTER (ADC) (Cont’d)10.8.3 Functional DescriptionThe conversion is monotonic, meaning that the re-sult never decreases

ST72325xx134/19710-BIT A/D CONVERTER (ADC) (Cont’d)10.8.6 Register DescriptionCONTROL/STATUS REGISTER (ADCCSR)Read/Write (Except bit 7 read only)Reset

ST72325xx135/19710-BIT A/D CONVERTER (Cont’d)Table 26. ADC Register Map and Reset Values Address(Hex.)RegisterLabel765432100070hADCCSRReset ValueEOC0S

ST72325xx136/19711 INSTRUCTION SET 11.1 CPU ADDRESSING MODESThe CPU features 17 different addressing modeswhich can be classified in seven main groups

ST72325xx137/197INSTRUCTION SET OVERVIEW (Cont’d)11.1.1 InherentAll Inherent instructions consist of a single byte.The opcode fully specifies all the

ST72325xx138/197INSTRUCTION SET OVERVIEW (Cont’d)11.1.6 Indirect Indexed (Short, Long)This is a combination of indirect and short indexedaddressing mo

ST72325xx139/197INSTRUCTION SET OVERVIEW (Cont’d)11.2 INSTRUCTION GROUPSThe ST7 family devices use an Instruction Setconsisting of 63 instructions. Th

ST72325xx14/19742 32 32 30 23 PC7/SS/AIN15 I/O CTX XXXXPort C7SPI Slave Select (ac-tive low)ADC Ana-logInput 1543 -4)---PA0 I/OCTX ei0 X X Port A044 -

ST72325xx140/197INSTRUCTION SET OVERVIEW (Cont’d)Mnemo Description Function/Example Dst Src I1 H I0 N Z CADC Add with Carry A = A + M + C A M H N Z CA

ST72325xx141/197INSTRUCTION SET OVERVIEW (Cont’d)Mnemo Description Function/Example Dst Src I1 H I0 N Z CJRULE Jump if (C + Z = 1) Unsigned <=LD Lo

ST72325xx142/19712 ELECTRICAL CHARACTERISTICS12.1 PARAMETER CONDITIONSUnless otherwise specified, all voltages are re-ferred to VSS.12.1.1 Minimum and

ST72325xx143/19712.2 ABSOLUTE MAXIMUM RATINGSStresses above those listed as “absolute maxi-mum ratings” may cause permanent damage tothe device. This

ST72325xx144/19712.2.3 Thermal Characteristics 12.3 OPERATING CONDITIONS12.3.1 General Operating ConditionsFigure 74. fCPU Max Versus VDD Note: Some

ST72325xx145/197OPERATING CONDITIONS (Cont’d)12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V

ST72325xx146/19712.4 SUPPLY CURRENT CHARACTERISTICSThe following current consumption specified for the ST7 functional operating modes over temperature

ST72325xx147/197SUPPLY CURRENT CHARACTERISTICS (Cont’d)12.4.2 Supply and Clock ManagersThe previous current consumption specified for the ST7 function

ST72325xx148/197SUPPLY CURRENT CHARACTERISTICS (Cont’d)12.4.3 On-Chip PeripheralsMeasured on LQFP64 generic board TA = 25°C fCPU=4MHz.Notes:1. Data ba

ST72325xx149/19712.5 CLOCK AND TIMING CHARACTERISTICSSubject to general operating conditions for VDD, fCPU, and TA.12.5.1 General Timings 12.5.2 Exte

ST72325xx15/197Table 3. LQFP32/DIP32 Device Pin Description Pin n°Pin NameTypeLevel PortMainfunction(afterreset)Alternate functionLQFP32DIP32InputOutp

ST72325xx150/197CLOCK AND TIMING CHARACTERISTICS (Cont’d)12.5.3 Crystal and Ceramic Resonator OscillatorsThe ST7 internal clock can be supplied with f

ST72325xx151/197Figure 76. Typical Application with a Crystal or Ceramic Resonator 1. The relatively low value of the RF resistor, offers a good prote

ST72325xx152/197CLOCK AND TIMING CHARACTERISTICS (Cont’d) Notes:1. Resonator characteristics given by the ceramic resonator manufacturer.2. SMD = [-R0

ST72325xx153/197CLOCK CHARACTERISTICS (Cont’d)12.5.4 RC Oscillators Figure 77. Typical fOSC(RCINT) vs TANote: To reduce disturbance to the RC oscillat

ST72325xx154/197CLOCK CHARACTERISTICS (Cont’d)12.5.5 Clock Security System (CSS) Note:1. Data based on characterization results.12.5.6 PLL Characteri

ST72325xx155/19712.6 MEMORY CHARACTERISTICS12.6.1 RAM and Hardware Registers 12.6.2 FLASH Memory Notes:1. Minimum VDD supply voltage without losing

ST72325xx156/19712.7 EMC CHARACTERISTICSSusceptibility tests are performed on a sample ba-sis during product characterization.12.7.1 Functional EMS (E

ST72325xx157/197EMC CHARACTERISTICS (Cont’d)12.7.2 Electro Magnetic Interference (EMI)Based on a simple application running on theproduct (toggling 2

ST72325xx158/197EMC CHARACTERISTICS (Cont’d)12.7.3 Absolute Maximum Ratings (ElectricalSensitivity)Based on two different tests (ESD and LU) usingspec

ST72325xx159/19712.8 I/O PORT PIN CHARACTERISTICS12.8.1 General CharacteristicsSubject to general operating conditions for VDD, fOSC, and TA unless ot

ST72325xx16/197Notes for Table 2 and Table 3:1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pul

ST72325xx160/197I/O PORT PIN CHARACTERISTICS (Cont’d)12.8.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unles

ST72325xx161/197I/O PORT PIN CHARACTERISTICS (Cont’d)Figure 84. Typical VOL vs. VDD (standard)Figure 85. Typical VOL vs. VDD (high-sink)Figure 86. Typ

ST72325xx162/19712.9 CONTROL PIN CHARACTERISTICS12.9.1 Asynchronous RESET PinSubject to general operating conditions for VDD, fCPU, and TA unless othe

ST72325xx163/197CONTROL PIN CHARACTERISTICS (Cont’d)Figure 87. RESET pin protection when LVD is enabled.1)2)3)4)Figure 88. RESET pin protection when L

ST72325xx164/197CONTROL PIN CHARACTERISTICS (Cont’d)12.9.2 ICCSEL/VPP PinSubject to general operating conditions for VDD, fCPU, and TA unless otherwis

ST72325xx165/19712.10 TIMER PERIPHERAL CHARACTERISTICSSubject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.Refer t

ST72325xx166/19712.11 COMMUNICATION INTERFACE CHARACTERISTICS12.11.1 SPI - Serial Peripheral InterfaceSubject to general operating conditions for VDD,

ST72325xx167/197COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)Figure 91. SPI Slave Timing Diagram with CPHA=11)Figure 92. SPI Master Timing Diagram

ST72325xx168/197COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)12.11.2 I2C - Inter IC Control InterfaceSubject to general operating conditions for VD

ST72325xx169/197COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)The following table gives the values to be written inthe I2CCCR register to obtain the

ST72325xx17/1973 REGISTER & MEMORY MAPAs shown in Figure 6, the MCU is capable of ad-dressing 64K bytes of memories and I/O registers.The availabl

ST72325xx170/19712.12 10-BIT ADC CHARACTERISTICSSubject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Notes:1. Any

ST72325xx171/197ADC CHARACTERISTICS (Cont’d)Figure 94. RAIN max. vs fADC with CAIN=0pF1)Figure 95. Recommended CAIN & RAIN values.2)Figure 96. Typ

ST72325xx172/197ADC CHARACTERISTICS (Cont’d)12.12.1 Analog Power Supply and ReferencePinsDepending on the MCU pin count, the packagemay feature separa

ST72325xx173/19710-BIT ADC CHARACTERISTICS (Cont’d)12.12.3 ADC AccuracyConditions: VDD=5V 1)Notes:1. ADC Accuracy vs. Negative Injection Current: Inje

ST72325xx174/19713 PACKAGE CHARACTERISTICS13.1 PACKAGE MECHANICAL DATA Figure 99. 64-Pin Low Profile Quad Flat Package (14x14)Dim.mm inches1)Min Typ M

ST72325xx175/197Figure 100. 64-Pin Low Profile Quad Flat Package (10 x10)Figure 101. 48-Pin Low Profile Quad Flat PackageDim.mm inches1)Min Typ Max Mi

ST72325xx176/197Figure 102. 44-Pin Low Profile Quad Flat PackageDim.mm inches1)Note 1. Values in inches are converted from mm and rounded to 4 decima

ST72325xx177/197PACKAGE MECHANICAL DATA (Cont’d)Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil WidthFigure 104. 32-Pin Plastic Dual I

ST72325xx178/197PACKAGE MECHANICAL DATA (Cont’d)Figure 105. 32-Pin Low Profile Quad Flat Package-Dim.mm inches1)Note 1. Values in inches are converte

ST72325xx179/19713.2 THERMAL CHARACTERISTICS Notes:1. The maximum chip-junction temperature is based on technology characteristics.2. The maximum pow

ST72325xx18/197Table 4. Hardware Register Map Address BlockRegister LabelRegister NameReset StatusRemarks0000h0001h0002hPort A PADRPADDRPAORPort A Da

ST72325xx180/19713.3 SOLDERING INFORMATION In order to meet environmental requirements,ST offers these devices in ECOPACK®packages. These packages ha

ST72325xx181/19714 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATIONEach device is available for production in user pro-grammable versions (FLASH)

ST72325xx182/197ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)OPT0= FMP_R Flash memory read-out protectionRead-out protection, when se

ST72325xx183/197ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODECustomer c

ST72325xx184/197Figure 106. Ordering information schemeST72 F 325 K 6 T 6FamilyST7 microcontroller familyMemory typeF: FlashBlank : ROMP = FASTROMMemo

ST72325xx185/197ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) ST72325 ROM MICROCONTROLLER OPTION LIST(Last update: October 2008)Custo

ST72325xx186/197DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)ST72P325 FASTROM MICROCONTROLLER OPTION LIST(Last update: October 2008)Customer:

ST72325xx187/19714.3 DEVELOPMENT TOOLSDevelopment tools for the ST7 microcontrollers in-clude a complete range of hardware systems andsoftware tools f

ST72325xx188/197DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)Table 31. Suggested List of Socket Types 14.3.4 Socket and Emulator AdapterInfo

ST72325xx189/19714.4 ST7 APPLICATION NOTES Table 32. ST7 Application NotesIDENTIFICATION DESCRIPTIONAPPLICATION EXAMPLESAN1658 SERIAL NUMBERING IMPLE

ST72325xx19/197002Ch002DhMCCMCCSRMCCBCRMain Clock Control / Status RegisterMain Clock Controller: Beep Control Register00h00hR/WR/W002Ehto0030hReserve

ST72325xx190/197AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARYGENERAL PURPOSEAN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCESAN1526 ST7FLI

ST72325xx191/197AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLERAN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7AN1179PR

ST72325xx192/19715 KNOWN LIMITATIONS15.1 ALL DEVICES15.1.1 Unexpected Reset FetchIf an interrupt request occurs while a “POP CC” in-struction is execu

ST72325xx193/197LD sema,AIRETCase 2: Writing to PxOR or PxDDR with Global In-terrupts Disabled:SIM ; set the interrupt maskLD A,PFDRAND A,#$02LD X,A

ST72325xx194/197KNOWN LIMITATIONS (Cont’d)15.1.4 SCI Wrong Break durationDescriptionA single break character is sent by setting and re-setting the SBK

ST72325xx195/197KNOWN LIMITATIONS (Cont’d)15.1.8 Pull-up always active on PE2 The I/O port internal pull-up is always active on I/Oport E2. As a resul

ST72325xx196/19716 REVISION HISTORYTable 33. Revision History Date Revision Description of Changes26-Sep-2005 1 Initial release04-Dec-2006 2Modified

ST72325xx197/197Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its su

Table of Contents1972/1971 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72325xx20/197Legend: x=undefined, R/W=read/writeNotes:1. The contents of the I/O port DR registers are readable only in output configuration. In inp

ST72325xx21/1974 FLASH PROGRAM MEMORY 4.1 IntroductionThe ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can beelectrical

ST72325xx22/197FLASH PROGRAM MEMORY (Cont’d)4.4 ICC Interface ICC needs a minimum of 4 and up to 6 pins to beconnected to the programming tool (see Fi

ST72325xx23/197FLASH PROGRAM MEMORY (Cont’d)4.5 ICP (In-Circuit Programming)To perform ICP the microcontroller must beswitched to ICC (In-Circuit Comm

ST72325xx24/1975 CENTRAL PROCESSING UNIT5.1 INTRODUCTIONThis CPU has a full 8-bit architecture and containssix internal registers allowing efficient 8

ST72325xx25/197CENTRAL PROCESSING UNIT (Cont’d)Condition Code Register (CC) Read/WriteReset Value: 111x1xxxThe 8-bit Condition Code register contains

ST72325xx26/197CENTRAL PROCESSING UNIT (Cont’d)Stack Pointer (SP)Read/WriteReset Value: 01 FFhThe Stack Pointer is a 16-bit register which is al-ways

ST72325xx27/1976 SUPPLY, RESET AND CLOCK MANAGEMENTThe device includes a range of utility features forsecuring the application in critical situations

ST72325xx28/1976.2 MULTI-OSCILLATOR (MO)The main clock of the ST7 can be generated bythree different source types coming from the multi-oscillator blo

ST72325xx29/1976.3 RESET SEQUENCE MANAGER (RSM)6.3.1 IntroductionThe reset sequence manager includes three RE-SET sources as shown in Figure 15: Exte

Table of Contents3/1978.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72325xx30/197RESET SEQUENCE MANAGER (Cont’d)The RESET pin is an asynchronous signal whichplays a major role in EMS performance. In a noisyenvironmen

ST72325xx31/1976.4 SYSTEM INTEGRITY MANAGEMENT (SI)The System Integrity Management block containsthe Low Voltage Detector (LVD) Auxiliary VoltageDetec

ST72325xx32/197SYSTEM INTEGRITY MANAGEMENT (Cont’d)6.4.2 Auxiliary Voltage Detector (AVD)The Voltage Detector function (AVD) is based onan analog comp

ST72325xx33/197SYSTEM INTEGRITY MANAGEMENT (Cont’d)6.4.2.2 Monitoring a Voltage on the EVD pinThis mode is selected by setting the AVDS bit inthe SICS

ST72325xx34/197SYSTEM INTEGRITY MANAGEMENT (Cont’d)6.4.3 Clock Security System (CSS)The Clock Security System (CSS) protects theST7 against breakdowns

ST72325xx35/197SYSTEM INTEGRITY MANAGEMENT (Cont’d)6.4.5 Register DescriptionSYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)Read/WriteReset Valu

ST72325xx36/1977 INTERRUPTS7.1 INTRODUCTIONThe ST7 enhanced interrupt management pro-vides the following features: Hardware interrupts Software inte

ST72325xx37/197INTERRUPTS (Cont’d)Servicing Pending Interrupts As several interrupts can be pending at the sametime, the interrupt to be taken into ac

ST72325xx38/197INTERRUPTS (Cont’d)7.3 INTERRUPTS AND LOW POWER MODESAll interrupts allow the processor to exit the WAITlow power mode. On the contrary

ST72325xx39/197INTERRUPTS (Cont’d)7.5 INTERRUPT REGISTER DESCRIPTIONCPU CC REGISTER INTERRUPT BITSRead/WriteReset Value: 111x 1010 (xAh)Bit 5, 3 = I1,

Table of Contents1974/19710.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72325xx40/197INTERRUPTS (Cont’d)Table 8. Dedicated Interrupt Instruction SetNote: During the execution of an interrupt routine, the HALT, POPCC, RIM

ST72325xx41/197INTERRUPTS (Cont’d)Table 9. Interrupt Mapping Notes:1. Exit from HALT possible when SPI is in slave mode.2. Exit from HALT possible whe

ST72325xx42/197INTERRUPTS (Cont’d)Figure 25. External Interrupt Control bitsIS10 IS11EICRSENSITIVITYCONTROLPBOR.3PBDDR.3IPB BITPB3ei2 INTERRUPT SOURCE

ST72325xx43/1977.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)Read/WriteReset Value: 0000 0000 (00h)Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivityThe inter

ST72325xx44/197INTERRUPTS (Cont’d)Table 10. Nested Interrupts Register Map and Reset Values Address(Hex.)RegisterLabel765432100024hISPR0Reset Valueei1

ST72325xx45/1978 POWER SAVING MODES8.1 INTRODUCTIONTo give a large measure of flexibility to the applica-tion in terms of power consumption, four main

ST72325xx46/197POWER SAVING MODES (Cont’d)8.3 WAIT MODEWAIT mode places the MCU in a low power con-sumption mode by stopping the CPU.This power saving

ST72325xx47/197POWER SAVING MODES (Cont’d)8.4 ACTIVE-HALT AND HALT MODESACTIVE-HALT and HALT modes are the two low-est power consumption modes of the

ST72325xx48/197POWER SAVING MODES (Cont’d)8.4.2 HALT MODEThe HALT mode is the lowest power consumptionmode of the MCU. It is entered by executing the‘

ST72325xx49/197POWER SAVING MODES (Cont’d)8.4.2.1 Halt Mode Recommendations– Make sure that an external event is available to wake up the microcontrol

Table of Contents5/19712.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14312.2.1 Vol

ST72325xx50/1979 I/O PORTS9.1 INTRODUCTIONThe I/O ports offer different functional modes:– transfer of data through digital inputs and outputsand for

ST72325xx51/197I/O PORTS (Cont’d)Figure 33. I/O Port General Block DiagramTable 11. I/O Port Mode OptionsLegend: NI - not implementedOff - implemente

ST72325xx52/197I/O PORTS (Cont’d)Table 12. I/O Port Configurations Notes:1. When the I/O port is in input configuration and the associated alternate f

ST72325xx53/197I/O PORTS (Cont’d)CAUTION: The alternate function must not be ac-tivated as long as the pin is configured as inputwith interrupt, in or

ST72325xx54/197I/O PORTS (Cont’d)9.5.1 I/O Port ImplementationThe I/O port register configurations are summa-rised as follows.Standard PortsPA5:4, PC7

ST72325xx55/197I/O PORTS (Cont’d)Table 14. I/O Port Register Map and Reset ValuesRelated DocumentationAN 970: SPI Communication between ST7 andEEPROMA

ST72325xx56/19710 ON-CHIP PERIPHERALS10.1 WATCHDOG TIMER (WDG)10.1.1 IntroductionThe Watchdog timer is used to detect the occur-rence of a software fa

ST72325xx57/197WATCHDOG TIMER (Cont’d)10.1.4 How to Program the Watchdog TimeoutFigure 2 shows the linear relationship between the6-bit value to be lo

ST72325xx58/197WATCHDOG TIMER (Cont’d)Figure 37. Exact Timeout Duration (tmin and tmax)WHERE:tmin0 = (LSB + 128) x 64 x tOSC2tmax0 = 16384 x tOSC2tOSC

ST72325xx59/197WATCHDOG TIMER (Cont’d)10.1.5 Low Power Modes10.1.6 Hardware Watchdog OptionIf Hardware Watchdog is selected by option byte,the watchdo

Table of Contents1976/19713.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18014

ST72325xx60/197Table 15. Watchdog Timer Register Map and Reset Values Address(Hex.)RegisterLabel76543210002AhWDGCRReset ValueWDGA0T61T51T41T31T21T11T0

ST72325xx61/19710.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)The Main Clock Controller consists of three differ-ent functions: a

ST72325xx62/197MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)10.2.5 Low Power Modes 10.2.6 InterruptsThe MCC/RTC interrupt event generates an int

ST72325xx63/197MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)Bit 0 = OIF Oscillator interrupt flagThis bit is set by hardware and cleared by soft

ST72325xx64/19710.3 PWM AUTO-RELOAD TIMER (ART)10.3.1 IntroductionThe Pulse Width Modulated Auto-Reload Timeron-chip peripheral consists of an 8-bit a

ST72325xx65/197ON-CHIP PERIPHERALS (Cont’d)10.3.2 Functional DescriptionCounterThe free running 8-bit counter is fed by the outputof the prescaler, an

ST72325xx66/197ON-CHIP PERIPHERALS (Cont’d)Independent PWM signal generationThis mode allows up to four Pulse Width Modulat-ed signals to be generated

ST72325xx67/197ON-CHIP PERIPHERALS (Cont’d)Output compare and Time base interruptOn overflow, the OVF flag of the ARTCSR registeris set and an overflo

ST72325xx68/197ON-CHIP PERIPHERALS (Cont’d)Input capture functionThis mode allows the measurement of externalsignal pulse widths through ARTICRx regis

ST72325xx69/197ON-CHIP PERIPHERALS (Cont’d)10.3.3 Register DescriptionCONTROL / STATUS REGISTER (ARTCSR)Read/WriteReset Value: 0000 0000 (00h) Bit 7 =

ST72325xx7/1971 DESCRIPTIONThe ST72F325 Flash and ST72325 ROM devicesare members of the ST7 microcontroller family de-signed for mid-range application

ST72325xx70/197ON-CHIP PERIPHERALS (Cont’d)PWM CONTROL REGISTER (PWMCR)Read/WriteReset Value: 0000 0000 (00h) Bit 7:4 = OE[3:0] PWM Output EnableThese

ST72325xx71/197ON-CHIP PERIPHERALS (Cont’d)INPUT CAPTURECONTROL / STATUS REGISTER (ARTICCSR)Read/WriteReset Value: 0000 0000 (00h) Bit 7:6 = Reserved,

ST72325xx72/197PWM AUTO-RELOAD TIMER (Cont’d)Table 17. PWM Auto-Reload Timer Register Map and Reset Values Address(Hex.)Register Label765432100073hPWM

ST72325xx73/19710.4 16-BIT TIMER10.4.1 IntroductionThe timer consists of a 16-bit free-running counterdriven by a programmable prescaler.It may be use

ST72325xx74/19716-BIT TIMER (Cont’d)Figure 45. Timer Block DiagramMCU-PERIPHERAL INTERFACECOUNTERALTERNATEOUTPUTCOMPAREREGISTEROUTPUT COMPAREEDGE DETE

ST72325xx75/19716-BIT TIMER (Cont’d)16-bit read sequence: (from either the CounterRegister or the Alternate Counter Register).The user must read the M

ST72325xx76/19716-BIT TIMER (Cont’d)Figure 46. Counter Timing Diagram, Internal Clock Divided by 2Figure 47. Counter Timing Diagram, Internal Clock Di

ST72325xx77/19716-BIT TIMER (Cont’d)10.4.3.3 Input CaptureIn this section, the index, i, may be 1 or 2 becausethere are two input capture functions in

ST72325xx78/19716-BIT TIMER (Cont’d)Figure 49. Input Capture Block DiagramFigure 50. Input Capture Timing Diagram ICIECC0CC116-BIT FREE RUNNINGCOUNTER

ST72325xx79/19716-BIT TIMER (Cont’d)10.4.3.4 Output Compare In this section, the index, i, may be 1 or 2 becausethere are two output compare functions

ST72325xx8/1972 PIN DESCRIPTION Figure 2. 64-Pin LQFP 14x14 and 10x10 Package PinoutVAREFVSSAVDD_3VSS_3MCO / AIN8 / PF0BEEP / (HS) PF1(HS) PF2OCMP2_A

ST72325xx80/19716-BIT TIMER (Cont’d)Notes: 1. After a processor write cycle to the OCiHR reg-ister, the output compare function is inhibiteduntil the

ST72325xx81/19716-BIT TIMER (Cont’d)Figure 52. Output Compare Timing Diagram, fTIMER =fCPU/2Figure 53. Output Compare Timing Diagram, fTIMER =fCPU/4IN

ST72325xx82/19716-BIT TIMER (Cont’d)10.4.3.5 One Pulse ModeOne Pulse mode enables the generation of apulse when an external event occurs. This mode is

ST72325xx83/19716-BIT TIMER (Cont’d)Figure 54. One Pulse Mode Timing ExampleFigure 55. Pulse Width Modulation Mode Timing Example with 2 Output Compar

ST72325xx84/19716-BIT TIMER (Cont’d)10.4.3.6 Pulse Width Modulation ModePulse Width Modulation (PWM) mode enables thegeneration of a signal with a fre

ST72325xx85/19716-BIT TIMER (Cont’d)10.4.4 Low Power Modes 10.4.5 Interrupts Note: The 16-bit Timer interrupt events are connected to the same interru

ST72325xx86/19716-BIT TIMER (Cont’d)10.4.7 Register DescriptionEach Timer is associated with three control andstatus registers, and with six pairs of

ST72325xx87/19716-BIT TIMER (Cont’d)CONTROL REGISTER 2 (CR2)Read/WriteReset Value: 0000 0000 (00h)Bit 7 = OC1E Output Compare 1 Pin Enable.This bit is

ST72325xx88/19716-BIT TIMER (Cont’d)CONTROL/STATUS REGISTER (CSR)Read/Write (bits 7:3 read only)Reset Value: xxxx x0xx (xxh)Bit 7 = ICF1 Input Capture

ST72325xx89/19716-BIT TIMER (Cont’d)INPUT CAPTURE 1 HIGH REGISTER (IC1HR)Read OnlyReset Value: UndefinedThis is an 8-bit read only register that conta

ST72325xx9/197Figure 3. 48-Pin LQFP 7x7 Device Pinout 44 43 42 41 40 39 38 3736353433323130292827262524231213 14 15 16 17 18 19 20 21 22123456 7 8 9 1

ST72325xx90/19716-BIT TIMER (Cont’d)OUTPUT COMPARE 2 HIGH REGISTER(OC2HR)Read/WriteReset Value: 1000 0000 (80h)This is an 8-bit register that contains

ST72325xx91/19716-BIT TIMER (Cont’d)Table 19. 16-Bit Timer Register Map and Reset Values Related DocumentationAN 973: SCI software communications usin

ST72325xx92/19710.5 SERIAL PERIPHERAL INTERFACE (SPI)10.5.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial

ST72325xx93/197SERIAL PERIPHERAL INTERFACE (Cont’d)–SS: Slave select:This input signal acts as a ‘chip select’ to letthe SPI master communicate with s

ST72325xx94/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.3.2 Slave Select ManagementAs an alternative to using the SS pin to control theSlave Select si

ST72325xx95/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.3.3 Master Mode OperationIn master mode, the serial clock is output on theSCK pin. The clock f

ST72325xx96/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.4 Clock Phase and Clock PolarityFour possible timing relationships may be chosenby software, u

ST72325xx97/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.5 Error Flags10.5.5.1 Master Mode Fault (MODF)Master mode fault occurs when the master deviceh

ST72325xx98/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.5.4 Single Master SystemsA typical single master system may be configured,using an MCU as the

ST72325xx99/197SERIAL PERIPHERAL INTERFACE (Cont’d)10.5.6 Low Power Modes10.5.6.1 Using the SPI to wakeup the MCU fromHalt modeIn slave configuration,