ADC 320F Specifications download pdf (Page 15)

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ADCINA0

ADCINA1

ADCINA7

MAX_CONV1

Ch Sel (CONV00)

Ch Sel (CONV01)

Ch Sel (CONV03)

Ch Sel (CONV02)

Ch Sel (CONV15)

State

pointer

12-bit

analog-to-digital

converter

(ADC)

SOC EOC

Analog MUX Result MUX

Result

select

ADCRESULT0

Autosequencer

state machine

Start-of-sequence trigger

Software

ePWMx SOCA

ePWMx SOCB

External pin

(GPIO/XINT2_ADCSOC)

MUX

select

Note: Possible values are:

Channel select = 0 to 15

ADCMAXCONV = 0 to 15

ADCRESULT1

ADCRESULT2

ADCRESULT15

MUX

select

ADCINB1

ADCINB7

MUX

select

ADCINB0

S/H-A

S/H-B

Autoconversion Sequencer Principle of Operation

Figure 1-4. Block Diagram of Autosequenced ADC in Cascaded Mode

SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) 15

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1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 45 46

Reference Guide 1
Contents 3
Read This First 7
Chapter 1 9
1.1 Features 10
Table 1-1. ADC Registers 11
Trim Register 12
Submit Documentation Feedback 13
A1/B1 channels 14
12-bit A/D 16
Sequencer arbiter 16
Example initialization: 18
Time-Sequenced Triggers) 21
1.4 ADC Clock Prescaler 26
1.5 Low-power Modes 26
1.6 Power-up Sequence 27
1.8 ADC Calibration 28
ADC Calibration 29
1.10 Offset Error Correction 31
1.11 ADC to DMA Interface 32
ADC Registers 33
2.1 ADC Control Registers 34
ADC Control Registers 35
Address 02h) 38
Trim Register (ADCOFFTRIM) 43
IMPORTANT NOTICE 46

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ADC 320F Specifications Page 15

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